Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity

A set of efficient algorithmic solutions suitable to the fully parallel hardware implementation short-length circular convolution cores is proposed. The advantage presented algorithms that they require significantly fewer multiplications as compared naive method implementing this operation. During synthesis algorithms, matrix notation cyclic operation was used, which made it possible represent using matrix–vector product. fact multiplicand a circulant allows its successful factorization, leads decrease in number when calculating such proposed are oriented towards completely implementation, but comparison with approach smaller hardwired multipliers. Since wired multiplier occupies much larger area on VLSI and consumes more power than adder, resource energy terms their implementation. We considered convolutions for sequences lengths N= 2, 3, 4, 5, 6, 7, 8, 9.